As the world’s appetite for bandwidth soars, the scale and complexity of modern data centers must grow to meet the demand. The data center network is evolving in multiple areas to meet the processing burden. Much attention has been focused on distributing the processing throughout the network fabric. One location in the fabric where programmable and intelligent processing has been added is the network interface card (NIC). NICs containing this added processing power are termed SmartNICs.
SmartNICs can be separated by implementation into 3 categories: those implemented with ASICs, those implemented with FPGAs, and those implemented with SOCs. Each of these implementations will have differing power needs depending on the silicon devices they employ but they will all share a common input voltage – +12V. Let’s take a look at an ASIC example from an actual design.
The example used here has 6 rails @1.8V and below. As previously stated, the input source is 12V. A simple way to step down from 12V to the other rails is to buck directly from 12V to the output voltages needed using single stage buck regulators. Two approaches come to mind. The first approach is to use all discrete converters with discrete inductors and capacitors. This approach can optimize efficiency at the expense of all other design factors, including board space and component count. A quality implementation of this approach for these 6 rails will yield in the neighborhood of 90% efficiency in a board space of 650-700 mm2 with approximately 90 components.
A second approach might be to apply some integration to the problem and use power modules with inductors integrated. This approach simplifies the design as the design engineer no longer needs to be involved in the engineering or sourcing effort to choose and layout components such as the inductors. At the same time, it reduces the component count and shrinks the design, but often at the expense of efficiency. A repute implementation will reduce board space to 500-550 mm2 and component count to approximately 40. Unfortunately, the efficiency trends downward as well. In this case, efficiency was calculated at 81%.
To summarize, the first approach optimizes efficiency at the expense of board space and component count, and the second approach optimizes simplicity and component count at the expense of efficiency. In contrast, Empower Semiconductor provides a unique third approach using Integrated Voltage Regulators (IVRs). With the Empower approach, we create a highly efficient 1.8V first stage that furnishes the 1.8V load and also supplies the inputs to the IVR devices which in turn create all of the sub-1.8V rails.
This approach represents a better compromise than the module approach previously presented because it only requires about 320 mm2 of board space and 12 components to implement. And the overall efficiency is a respectable 86%.
With designers continually being asked to pack more functionality into less space, power supply designs are being squeezed like never before. Traditional buck regulator technology trades size for efficiency. Empower IVRs can avoid this compromise and offer the best of both worlds.