2:00PM – 2:45PM | Ballroom A |
Luca Vassalli presents on supercharging SoC power integrity with silicon capacitors.
The rise of AI and high-performance computing (HPC) is pushing the limits of power delivery design. As xPUs grow in complexity, power density, and I/O bandwidth, maintaining power integrity across system-level platforms becomes increasingly difficult. Traditional power delivery networks (PDNs), which rely heavily on ceramic decoupling capacitors are now reaching fundamental limitations. Chief among these is parasitic inductance, particularly equivalent series inductance (ESL), which leads to impedance peaking at mid-frequencies and degrades overall system performance.
This paper introduces silicon capacitors as a breakthrough solution to these power integrity challenges. Offering almost ideal ESL, ultra-thin profiles, and flexible integration into package substrates, silicon capacitors significantly flatten PDN impedance and suppress mid-frequency noise that conventional approaches fail to address. These devices enable proximity decoupling directly at the point of load, improving transient response and unlocking performance in dense chiplet-based architectures.
System-level PDN models, impedance vs. frequency comparisons, and cross-sectional package diagrams will be presented, to illustrate capacitor placement strategies. Application-specific examples—including real product imagery—will demonstrate the practical benefits of silicon capacitors in designs. The configurability of silicon capacitors in terms of thickness, termination types, and form factors will also be discussed to support implementation across varied packaging platforms.